There are three parasitic capacitance parameters in the MOS transistor specification book, namely: input capacitance Ciss, output capacitance Coss, and reverse transmission capacitance Crss. What do these three capacitor parameters represent specifically in the body of the tube? How was it formed?

The core of power semiconductors is the PN junction, and various applications such as diodes, transistors, and field-effect transistors are made based on the characteristics of the PN junction. Field effect transistors are divided into junction type and insulated gate type, among which insulated gate type is also known as MOS transistor (Metal Oxide Semiconductor).

According to whether the inversion layer exists in the absence of power, MOS transistors can be divided into enhancement type and depletion type

Reasons for the formation of parasitic capacitance

1. Barrier capacitance: In power semiconductors, when N-type and P-type semiconductors are combined, due to the concentration difference, some electrons from the N-type semiconductor will diffuse into the holes of the P-type semiconductor. Therefore, space charge regions will be formed on both sides of the joint surface (the electric field formed by this space charge region will cause resistance diffusion motion, ultimately achieving equilibrium diffusion motion);

2. Diffusion capacitance: When a forward voltage is applied, the concentration of non-equilibrium minority carriers near the depletion layer interface is high, while the concentration of non-equilibrium minority carriers far away is low, and the concentration gradually decreases from high to low until 0. When the applied forward voltage increases, the concentration of non-equilibrium minority carriers increases and the concentration gradient also increases. When the applied voltage decreases, the change is opposite. The process of charge accumulation and release in this phenomenon is the same as the charging and discharging process of capacitors, which is called diffusion capacitance.

The parasitic capacitance structure of MOS transistor is as follows, among which the width of polycrystalline silicon, the width of channel and trench, the thickness of G-electrode oxide layer, and the doping profile of PN junction are all factors that affect the parasitic capacitance.

For the definition of the three capacitance parameters in the MOS transistor specification book,

Input capacitance Ciss=Cgs+Cgd;

Output capacitance Coss=Cds+Cgd;

Reverse transmission capacitance Crss=Cgd

These three capacitors are almost unaffected by temperature changes, therefore, the driving voltage and switching frequency will significantly affect the switching characteristics of MOS transistors, while the influence of temperature is relatively small.